FinFETs provide superior levels of scalability and increased levels of integration within integrated circuits. The FinFET, for example, also provides improved electrical control over the channel conduction and reduced leakage current levels. Moreover, the FinFET can overcome some other short-channel effects. In addition, FinFETs can provide lower power consumption which allows high integration levels, operation at lower voltage as a result of their lower threshold voltage and, often, increase operating speeds compared to planar devices.
As the FinFET scales down, it is critical to control the spacer thickness between NFET and PFET devices. For example, an increased spacer thickness on one type of device may effectively limit the scaling of the entire device structure. This poses a problem in current technology nodes and beyond, in which process of record fabrication processes require spacer deposition to protect PFET devices during epitaxy processes, leading to an increased spacer thickness for the PFET device. That is, the additional spacer leads to different spacer thickness between the NFET device and the PFET device. This additional spacer thickness which requires additional space between devices becomes ever more critical in advanced technology nodes that have limited space between devices.